With the rapid development of semiconductor technologies, the growth of access bandwidth of storage devices (such as a hard disk) that use magnetic media to record information has fallen far behind the increase of processing speeds of processors. Meanwhile, for various non-volatile storage technologies that are based on semiconductor technologies, such as flash memories and other storage devices, the capacity is continuously raised, the cost is continuously reduced, and the performance-to-cost ratio is continuously improved. Under such a development tendency, non-volatile storage devices based on semiconductors are gradually replacing conventional storage devices based on magnetic media to become main storage devices. Current non-volatile storage devices have an asymmetric read/write feature, and in fact, when a non-volatile storage device is used, a read operation delay is much shorter than a write operation delay.
Although a non-volatile storage device is superior to a conventional storage device in both access delay and actual bandwidth, it is still inferior to a memory, let alone an on-chip cache of a processor. Therefore, an intermediate storage layer (main memory or processor on-chip cache) is needed to serve as a cache between a processor and a non-volatile storage device to improve the actual access bandwidth of the non-volatile storage device.
A cache design scheme specific to conventional storage devices is optimized with a core objective to improve a cache hit rate, and when directly applied to a storage architecture that uses a non-volatile storage device, it results in such problems as an increased average read/write delay due to frequent replacement of dirty pages and a reduced service life of the device. Moreover, if a complex cost model is applied to the storage architecture that uses a non-volatile storage device, the implementation cost is high and the execution efficiency is low.